The present invention relates to an error correction method using an apparatus for correcting errors in received information data and the error correction apparatus. More particularly, it relates to an error correction method and an error correction apparatus for correcting errors in information data to which error-correcting codes comprising a product code having inner codes and outer codes are added.
Initially, a prior art error correction apparatus is described.
FIG. 9 is a block diagram illustrating a structure of the prior art error correction apparatus 50.
The error correction apparatus 50 has a format interface 10 for executing demodulation processing for serial data 100 from an optical disk playback apparatus 6 and outputting demodulated data, a buffer memory 32 containing the demodulated data, an error correction circuit 20 for executing decoding including syndrome operation for the error-correcting codes, using the demodulated data from the format interface 10 or buffer memory 32, a buffer memory manager 31 for controlling writing of the demodulated data onto the buffer memory 32 and reading of the demodulated data out of the buffer memory 32, a descrambling circuit 33 for executing descrambling processing for demodulated data 300 which are read out of the buffer memory 32, a data transfer circuit 34 for transferring data 301 from the descrambling circuit 33 after being subjected to the descrambling processing to an external apparatus as transfer data 302, and a microcontroller 40 for outputting control signals to the respective circuits in the error correction apparatus 50 to control the whole operation of the error correction apparatus 50.
The format interface 10 has a Sync code detection and removal circuit 11 for converting the received serial data 100 in parallel, to detect frame Sync codes, synchronizing the received data, and then removing the frame Sync codes, and a demodulation circuit 12 for executing the demodulation processing for information data 102 from the Sync code detection and removal circuit 11.
The error correction circuit 20 has a first syndrome operation circuit 21 for executing syndrome operation for the demodulated data 106 from the demodulation circuit 12, a second syndrome operation circuit 22 for executing syndrome operation for the demodulated data from the buffer memory 32, a syndrome selection circuit 23 for selecting the syndrome operation result of one of the first and second syndrome operation circuits 21 and 22 and outputting the selected result, a Eucledean algorithm operation circuit 24 for deriving an error location polynomial and an error value polynomial on the basis of the syndrome operation result 202 from the syndrome selection circuit 23, a chain search circuit 25 for calculating an error location from the degree of the error location polynomial, an error value operation circuit 26 for calculating an error value from the degree of the error value polynomial, an address generation circuit 27 for converting the calculated error location into a logical address 206 on the buffer memory 32, and an error correction circuit 28 for reading data 207 at the logical address 206 which is output by the address generation circuit 27 and executing error correction.
That is, the error correction apparatus 50 judges whether errors are included in the received data on the basis of the operation result of the syndrome operation which is executed for the demodulated data, and judges whether the errors included in the received data are correctable errors on the basis of the degree of the error location polynomial which is derived from the syndrome operation result. When the errors included in the received data are correctable, the error location and error value are respectively obtained from the derived error location polynomial and error value polynomial, thereby to correct the errors in the received data.
In addition, the error correction apparatus 50 is constructed so that the demodulation of the received data and the decoding of the demodulated data is executed in the same order as the order in which the received data are received. Here, the description is given assuming that the error correction of inner codes is initially executed.
Next, prior art error correction processing is described with reference to a flowchart of FIG. 8.
Initially in STEP 10, when the serial data 100 (referred to also as received data) are input to the error correction apparatus 50, synchronization of the received data is protected by the Sync code detection and removal circuit 11. Then, in parallel with the demodulation processing in the demodulation circuit 12, the syndrome operation is executed for the demodulated data 106 from the demodulation circuit 12 by the first syndrome operation circuit 21.
In STEP 13, it is judged whether a code length of data has been processed. When it is in the middle of the processing, the processing branches to LOOP 10 and the syndrome operation is continued. For example, in the case of the inner code of DVD as shown in FIG. 6, the code length of the received data is 182 bytes. When the processing for the code length of the data is completed, the processing proceeds to STEP 20.
In STEP 20, it is judged by the Eucledean algorithm operation circuit 24 whether there are errors in the received data on the basis of whether the result 200 of the syndrome operation from the first syndrome operation circuit 21 is zero. When the operation result 200 is zero, no error is included in the data and therefore the error correction processing is terminated.
When errors are included in the data, the processing proceeds to STEP 21. In STEP 21, the error value polynomial and the error location polynomial are derived by the Eucledean algorithm operation circuit 24.
In the following STEP 22, it is initially judged whether the errors included in the received data are capable of error correction on the basis of the degree of the error location polynomial (which indicates the number of the errors).
In the case of the inner code of DVD, 10 bytes of parity data are added and it has a 5-byte error correction capability. When this error correction capability is exceeded, the error correction is incapable. Therefore, the error correction processing of the inner codes is terminated.
When the errors included in the received data are capable of error correction, the processing proceeds to the following STEP 23. In STEP 23, the error location 204 is obtained from the coefficients of the error location polynomial by the chain search circuit 25. This error location 204 is converted into the logical address 206 on the buffer memory 32 by the address generation circuit 27 and stored in the buffer memory 32, and then the processing proceeds to STEP 24.
In STEP 24, the error value 205 is obtained from the coefficients of the error value polynomial by the error value operation circuit 26 as well as the logical address 206 of the error location, which is obtained in the previous STEP 23, is read out of the buffer memory 32. The error correction is executed for the read data 207 on the basis of the error value 205.
In the next STEP 25, when the degree of the error correction has been completed, the error correction processing of the inner codes is terminated. When it is in the middle of the error correction processing, the processing proceeds to LOOP 21 and the error correction for the remaining errors is continued.
Thus, in the prior art error correction method, the error location polynomial is obtained and the judgement as to whether errors included in the received data are capable of error correction can be made only on the basis of the degree of the obtained polynomial.
The erasure correction of the outer codes is executed when the degree of the error location polynomial derived by the Eucledean algorithm operation circuit 24 exceeds the error correction capability using the information of rows which were incapable of error correction, being obtained during the error correction of the inner codes.
Another error correction apparatus is disclosed in Japanese Published Application No. Hei. 8-130480. This xe2x80x9cerror correction decoderxe2x80x9d judges whether there are errors and whether the errors are correctable using the result of the syndrome operation, and executes control as to whether the subsequent error correction processing is to be executed on the basis of the judgement result.
As described above, the prior art error correction apparatus uses the operation result of the syndrome operation or derives the error location polynomial and thereby uses the degree of the obtained polynomial to make the judgement as to whether the errors are capable of error correction. However, the method of judging whether the errors are capable of error correction on the basis of the operation result of the syndrome operation can be applied only to a code having a lower error correction capability. Accordingly, this method cannot be applied to codes of DVD or the like, having a higher error correction capability, to realize high-density recording. In addition, in the method of deriving the error location polynomial and make the judgement as to whether the errors are capable of error correction on the basis of the degree of the obtained polynomial, unnecessary processing of STEPs 21 and 22 following the syndrome operation is executed even when uncorrectable errors are included in the received data.
Further, in the prior art error correction apparatus, the erasure correction of the outer codes is executed using the information of rows which were incapable of the error correction, being obtained at the time when the inner code is decoded. However, the information of the rows which is obtained at the decoding time of the inner code has lower precision as the information for estimating the error location when the erasure correction of the outer codes is executed. Therefore, the error correction capability cannot be increased.
It is an object of the present invention to provide a method and apparatus for error correction having a good error correction capability, which can detect whether errors in the received data are correctable errors without deriving the error location polynomial also for a code having a higher error correction capability, and does not execute unnecessary syndrome operations and processing subsequent to the syndrome operation.
An error correction apparatus according to a first aspect of the present invention comprises: information data demodulation means for executing demodulation processing for information data to which error-correcting codes are added, to output demodulated data as well as detecting an uncorrectable error from the information data in parallel with the demodulation processing; and correction decoding means for executing decoding of error correction, including syndrome operation, for the demodulated data from the information data demodulation means as well as suspending the syndrome operation when the uncorrectable error is detected by the information data demodulation means. Therefore, unnecessary syndrome operation is not executed, whereby the power consumption can be reduced. Further, the hardware resources can be effectively utilized, thereby increasing the error correction performance.
According to a second aspect of the present invention, in the error correction apparatus of the first aspect, the information data to which the error-correcting codes are added comprise a product code having inner codes in a row direction and outer codes in a column direction, and the correction decoding means executes the error correction decoding for the demodulated data from the information data demodulation means in the same order as that of the demodulation in the information data demodulation means. Therefore, the error detection information at the demodulation time can be utilized for the erasure correction of the information data in a direction different from that of the demodulation.
According to a third aspect of the present invention, in the error correction apparatus of the first or second aspect, the information data demodulation means comprises: Sync code detection and removal means for receiving the information data, converting the received data in parallel, detecting a frame Sync code, synchronizing the received data, and then removing the frame Sync code, as well as counting a number of the received data in one SYNC frame; demodulation means for executing demodulation processing for the received data from the Sync code detection and removal means; a number-of-missing-data counter for counting a number of missing data in a predetermined code length of data on the basis of the number of the received data from the Sync code detection and removal means; an inhibition pattern detector/counter for detecting abnormal patterns which do not conform a predetermined modulation rule from the received data which are output from the Sync code detection and removal means, and counting a number of inhibition patterns; and error correction incapability judge means for judging whether an uncorrectable error is included in the information data on the basis of the number of missing data obtained by the number-of-missing-data counter and the number of inhibition patterns obtained by the inhibition pattern detector/counter, and outputting an error correction incapability detection signal when the uncorrectable error is included. Therefore, also for the codes having a higher error correction capability, the errors exceeding the correction capability can be detected from the received data without solving the error location polynomial. Accordingly, unnecessary syndrome operation can be omitted, whereby the power consumption can be reduced. Further, the hardware resources can be effectively utilized, thereby improving the error correction performance.
According to a fourth aspect of the present invention, in the error correction apparatus of one of the first through third aspects, storage means which contains demodulated data are provided, and the correction decoding means comprises: first syndrome operation means for executing syndrome operation for the demodulated data output from the demodulation means; second syndrome operation means for executing syndrome operation for the demodulated data output from the storage means; syndrome selection means for selecting one of syndrome operation results of the first and second syndrome operation means and outputting the selected syndrome operation result; error detection means for calculating an error location and an error value on the basis of the syndrome operation result output from the syndrome selection means; and correction means for correcting errors in the received information data on the basis of the error location and the error value. Therefore, unnecessary syndrome operation and the processing subsequent to the syndrome operation are not executed, thereby reducing the power consumption. Further, the hardware resources can be effectively utilized, whereby the error correction performance can be increased.
According to a fifth aspect of the present invention, in the error correction apparatus of the third aspect, when there is data missing in the information data, the means interpolates data of the missing on the number of the missing data, obtained by the number-of-missing-data counter, and makes the information have the predetermined code length. Therefore, even when there is data missing due to bit slip or the like, the received data always have a predetermined length. Accordingly, when data are stored in the buffer memory, the data can be written in a contiguous area.
According to a sixth aspect of the present invention, in the error correction apparatus of the third aspect, when there is data missing in the information data, the Sync code detection and removal means execute interpolation of the data missing using the inhibition patterns under the modulation rule, the inhibition pattern detector/counter detects the inhibition patterns in the information data for which the data missing is interpolated by the Sync code detection and removal means, and the error correction incapability judge means judges whether the error correction is possible, only on the basis of whether the number of inhibition patterns obtained by the inhibition pattern detector/counter exceeds error correction capability of the information data. Therefore, the number-of-missing-data counter is not required. Thus, the error correction incapability judge means detects uncorrectable errors only from the output of the inhibition pattern counter.
According to a seventh aspect of the present invention, in the error correction apparatus of the third aspect, erasure correction information storage means are provided, which when it is judged by the error correction incapability judge means that an uncorrectable error is included in the information data in the same direction as that of the demodulation, contain location information of correction incapability of the error judged to be uncorrectable, as first erasure correction information, and when the information is decoded in a direction different from that of the demodulation, the erasure correction information storage means judges whether erasure correction is possible from whether the number of error correction incapabilities in the information data in the same direction as that of the demodulation, as the number of erasures, exceeds erasure correction capability of the information data in the direction different from that of the demodulation, on the basis of the first erasure correction information which is stored in the means when the information data are decoded in a direction different from that of the demodulation, and controls the execution of the erasure correction on the basis of the judgement result. Therefore, unnecessary syndrome operation and the processing subsequent to the syndrome operation is not executed, whereby the power consumption can be reduced. Further, the hardware resources can be effectively utilized, thereby improving the error correction performance.
According to an eighth aspect of the present invention, in the error correction apparatus of the fourth or seventh aspect, the storage means contains the location information of the error correction incapability obtained when the error location is detected by the error detection means, as second erasure correction information, and the correction decoding means selects optimum erasure correction information from the first erasure correction information which is stored in the erasure correction information storage means and the second erasure correction information which is stored in the storage means when the erasure correction of the information data in the direction different from that of the demodulation is possible, and use the selected erasure correction information for the erasure correction. Therefore, information which has a narrower range and a higher precision than those of the conventional incapability information at the decoding can be utilized, whereby the error correction capability can be increased.
According to a ninth aspect of the present invention, in the error correction apparatus of the fourth aspect, the first syndrome operation means suspends the syndrome operation as well as nullify the syndrome operation result, when the error correction incapability detection signal is input by the error correction incapability judge means during the syndrome operation, and the error detection means does not execute the calculation of the error location and the error value when the syndrome operation result is zero. Therefore, unnecessary syndrome operation and processing subsequent to the syndrome operation are not executed, whereby the power consumption can be reduced. Further, the hardware resources can be effectively utilized, whereby the error correction performance can be increased.
According to a tenth aspect of the present invention, in the error correction apparatus of the fourth aspect, control means for controlling a series of operations of the syndrome operation, the calculation of the error location and the error value, and the error correction are provided, and the control means performs controls so as to execute none or part of the series of the operations of the syndrome operation, the calculation of the error location and the error value, and the error correction in the correction means, when the error correction incapability detection signal is input to the correction means by the error correction incapability judge means. Therefore, the unnecessary syndrome operation and the processing subsequent to the syndrome operation are not executed, whereby the power consumption can be reduced. Further, the hardware resources can be effectively utilized, thereby improving the error correction performance.
An error correction method according to an eleventh aspect of the present invention comprises: a counting step of, when demodulation processing is executed for information data to which error correcting-codes are added, detecting whether there are inhibition patterns which do not conform a modulation rule of the information data and there is data missing in a SYNC frame, and counting a number of the inhibition patterns and the missing data, respectively; a judging step of detecting errors which are incapable of error correction from the information data on the basis of the number of the missing data and the number of the inhibition patterns, and judging whether the detected errors are capable of the error correction, an error correction step of executing error correction processing, when the judgement result of the error correction indicates that the error correction is capable; and a terminating step of terminating a series of the error correction processing, when the judgement result of the error correction indicates that the error correction is incapable or when the error correction is completed, and judging whether error correction of the information data is possible or not prior to the error correction processing, and controlling the error correction processing on the basis of the judgement result. Therefore, unnecessary syndrome operation and the processing subsequent to the syndrome operation are not executed, thereby reducing the power consumption. Further, the hardware resources can be effectively utilized, whereby the error correction performance can be improved.
According to a twelfth aspect of the present invention, the error correction method of the eleventh aspect comprises: a first storage step of, when it is judged in the judging step that the errors included in the information data are incapable of the error correction, storing location information of error correction incapability as first erasure correction information; a second storage step of storing location information of error correction incapability, which is obtained in the error correction step during the error correction, as second erasure correction information, and an erasure correction step of executing erasure correction of the information data in a direction different from that of the demodulation, using the first and second erasure correction information which is stored in the first and second storage steps. Therefore, the information which has a narrower range and a higher precision than those of the conventional correction incapability information at the decoding can be utilized, whereby the error correction performance can be increased.